Design and Performance Analysis of Fixed-point Jacobi SVD Algorithm on Reconfigurable System
2014
Mohanty, Ramanarayan | Anirudh, Gonnabhaktula | Pradhan, Tapan | Kabi, Bibek | Routray, Aurobinda
This paper presents design and performance analysis of fixed-point two sided Jacobi Singular Value Decomposition (SVD) algorithm on reconfigurable system using pipelined state-of-the-art CORDIC architecture. The algorithm has been implemented in reconfigurable hardware with the proposed architecture to achieve faster performance for matrices with larger dimensions. This design has not only reduced the computational complexity but also exploited parallelism in data transfer methods. Various quantization modes along with their range of relative errors are discussed. A comparative study of execution time shows that FPGA implementation with increasing dimension is found to be superior to its floating-point counterpart. Accuracy of FPGA and SystemC based fixed-point implementation is compared based on number of accurate fractional bits, signal-to-quantization-noise-ratio (SQNR), orthogonality and factorization errors with respect to double precision floating-point results.
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